Vahid Lari

According to our database, Vahid Lari authored at least 23 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.

Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel

IEEE Trans. Computers, 2017

2016

Invasive tightly coupled processor arrays = Invasive eng gekoppelte Prozessorfelder.

Vahid Lari

PhD thesis, 2016

Providing fault tolerance through invasive computing.

Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker

it Inf. Technol., 2016

2015

Resource-awareness on heterogeneous MPSoCs for image processing.

Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel

J. Syst. Archit., 2015

Techniques for on-demand structural redundancy for massively parallel processor arrays.

Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer

J. Syst. Archit., 2015

On-demand fault-tolerant loop processing on massively parallel processor arrays.

Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Adaptive fault tolerance through invasive computing.

Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.

Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.

Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche

ACM Trans. Embed. Comput. Syst., 2014

Massively Parallel Processor Architectures for Resource-aware Computing.

Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich

CoRR, 2014

Self-adaptive harris corner detector on heterogeneous many-core processor.

Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms.

Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich

Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.

Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich

Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

System integration of tightly-coupled processor arrays using reconfigurable buffer structures.

Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich

Proceedings of the Computing Frontiers Conference, 2013

2012

Hierarchical power management for adaptive tightly-coupled processor arrays.

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich

ACM Trans. Design Autom. Electr. Syst., 2012

A prototype of an invasive tightly-coupled processor array.

Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Invasive manycore architectures.

Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design of Low Power On-chip Processor Arrays.

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Distributed Resource Reservation in Massively Parallel Processor Arrays.

Vahid Lari, Frank Hannig, Jürgen Teich

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Decentralized dynamic resource management support for massively parallel processor arrays.

Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2009

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.

Vahid Lari, Frank Hannig, Jürgen Teich

Proceedings of the ICPPW 2009, 2009

2008

Fault Effects in FlexRay-Based Networks with Hybrid Topology.

Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi

Proceedings of the The Third International Conference on Availability, 2008

2007

Assessment of Message Missing Failures in FlexRay-Based Networks.

Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand

Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007