Vadthiya Narendar

According to our database, Vadthiya Narendar authored at least 5 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis.

Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad

Microelectron. J., 2024

2023

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes.

Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar

Microelectron. J., December, 2023

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications.

Ravi Kothapally, Vadthiya Narendar, Satish Maheshwaram

Microelectron. J., December, 2023

2022

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis.

Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad

Microelectron. J., 2022

2021

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes.

V. Bharath Sreenivasulu, Vadthiya Narendar

Microelectron. J., 2021