V. Visvanathan

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2015
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications.
J. Low Power Electron., 2015

2014
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions.
J. Low Power Electron., 2013

2012
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs.
J. Low Power Electron., 2012

2010
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.
J. Low Power Electron., 2008

Within-die gate delay variability measurement using re-configurable ring oscillator.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005
Application of Alpha Power Law Models to PLL Design Methodology.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2001
CMOS op-amp sizing using a geometric programming formulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Reconfigurable Filter Coprocessor Architecture for DSP Applications.
J. VLSI Signal Process., 2000

1999
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering.
J. VLSI Signal Process., 1999

A computational engine for multirate FIR digital filtering.
Signal Process., 1999

Synthesis of ASIPs for DSP algorithms.
Integr., 1999

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1.
Integr., 1999

Synthesis of Configurable Architectures for DSP Algorithms.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A New Approach for CMOS Op-Amp Synthesis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.
Proceedings of the IEEE International Conference On Computer Design, 1999

1997
Low-Power Configurable Processor Array for DLMS Adaptive Filtering.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Self-Biased High Performance Folded Cascode CMOS Op-Amp.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
A systolic architecture for LMS adaptive filtering with minimal adaptation delay.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Design of high performance two stage CMOS cascode op-amps with stable biasing.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

VLSI Implementation of DSP Architectures.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
A modular systolic architecture for delayed least mean squares adaptive filtering.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994
High Speed Digital Filtering on SRAM-Based FPGAs.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A CORDIC Based Programmable DXT Processor Array.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.
IEEE Trans. Very Large Scale Integr. Syst., 1993

An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Methodology for Generating Application Specific Tree Multipliers.
Proceedings of the Sixth International Conference on VLSI Design, 1993

NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Macromodeling of the A.C. characteristics of CMOS Op-amps.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991
Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1991

1989
Efficient sparse matrix factorization for circuit simulation on vector supercomputers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Detection of catastrophic faults in analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A Framework for Scheduling Multi-Rate Circuit Simulation.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Circuit Simulation on Shared-Memory Multiprocessors.
IEEE Trans. Computers, 1988

Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor.
Proceedings of the 2nd international conference on Supercomputing, 1988

Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1986
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
Proceedings of the Second Annual ACM SIGACT/SIGGRAPH Symposium on Computational Geometry, 1986

1984
A Computational Approach for the Diagnosability of Dynamical Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1981
Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case.
IEEE Trans. Computers, 1981

Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems.
IEEE Trans. Computers, 1981


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