V. Moroz

According to our database, V. Moroz authored at least 3 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Through silicon via to FinFET noise coupling in 3-D integrated circuits.

A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2011

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.

Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas

Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.

Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011