V. K. Agrawal

According to our database, V. K. Agrawal authored at least 19 papers between 1985 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Hardware implementation of support vector machine classifier using reconfigurable architecture.

Santosh Kumar, J. Manikandan, V. K. Agrawal

Proceedings of the 2017 International Conference on Advances in Computing, 2017

2015

Design and evaluation of FPGA based frequency demodulators.

Senthilkumar E., J. Manikandan, V. K. Agrawal

Proceedings of the 2015 International Conference on Advances in Computing, 2015

2014

MATLAB-Based GUI Development for Stochastic Noise Analysis of Tri-Axial Gyroscopes.

A. Divya Rao, Piyush Kumar, Neha Nain, V. K. Agrawal

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

FPGA implementation of dynamically tunable filters.

Senthilkumar E., J. Manikandan, V. K. Agrawal

Proceedings of the 2014 International Conference on Advances in Computing, 2014

2013

Design and Evaluation of N-Module Reconfigurable Systems.

Kunal Yogeshkumar Parikh, J. Manikandan, V. K. Agrawal

Proceedings of the Intelligent Computing, 2013

Design of a Biometric Security System Using Support Vector Machine Classifier.

J. Manikandan, V. K. Agrawal, B. Venkataramani

Proceedings of the Intelligent Computing, 2013

2008

Software-Based Resolver-to-Digital Conversion Using a DSP.

Santanu Sarma, V. K. Agrawal, Subramanya Udupa

IEEE Trans. Ind. Electron., 2008

2007

A New ATPG Technique (ExpoTan) for Testing Analog Circuits.

B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2004

A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.

B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A simple scheme for PSK demodulation.

P. Balasubramanian, P. M. Aravindakshan, K. Parameswaran, V. K. Agrawal

Microprocess. Microsystems, 2004

2001

An Efficient Test Pattern Generation Scheme for an On Chip BIST.

B. K. S. V. L. Varaprasad, L. M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal

VLSI Design, 2001

Genetic programming based pattern classification with feature space partitioning.

J. K. Kishore, Lalit M. Patnaik, V. Mani, V. K. Agrawal

Inf. Sci., 2001

2000

Application of genetic programming for multicategory pattern classification.

J. K. Kishore, Lalit M. Patnaik, V. Mani, V. K. Agrawal

IEEE Trans. Evol. Comput., 2000

A hardware/software codesign for improved data acquisition in a processor based embedded system.

F. Thomas, M. M. Nayak, Subramanya Udupa, J. K. Kishore, V. K. Agrawal

Microprocess. Microsystems, 2000

1999

Design and implementation of a wheel speed measurement circuit using field programmable gate arrays in a spacecraft.

F. Thomas, J. K. Kishore, K. M. Bharadwaj, M. M. Nayak, V. K. Agrawal

Microprocess. Microsystems, 1999

1994

A Real Time Fault Tolerant Microprocessor Based On-Board Computer System for INSAT-2 Spacecraft.

J. K. Kishore, R. S. Manjunatha, V. K. Agrawal, N. K. Malik, Prem Shankar Goel

Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, Third International Symposium Organized Jointly with the Working Group Provably Correct Systems, 1994

1991

Extended colored Petri net: An efficient tool for analyzing concurrent systems.

Sajal K. Das, Dilip Sarkar, V. K. Agrawal, Lalit M. Patnaik

Inf. Sci., 1991

1987

Reflexive Incidence Matrix (RIM) Representation of Petri Nets.

Sajal K. Das, V. K. Agrawal, Dilip Sarkar, Lalit M. Patnaik, Prem Shankar Goel

IEEE Trans. Software Eng., 1987

1985

Towards formal specification of a distributed computing system.

V. K. Agrawal, Lalit M. Patnaik, Prem Shankar Goel

Int. J. Parallel Program., 1985