V. Deshpande

According to our database, V. Deshpande authored at least 3 papers between 2017 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling.

A. Vandooren, Liesbeth Witters, Jacopo Franco, Arindam Mallik, Bertrand Parvais, Z. Wu, Amey Walke, V. Deshpande, E. Rosseel, Andriy Hikavyy, W. Li, L. Peng, Nouredine Rassoul, Geraldine Jamieson, Fumihiro Inoue, G. Verbinnen, Katia Devriendt, Lieve Teugels, N. Heylen, E. Vecchio, T. Zheng, Niamh Waldron, Vincent De Heyn, Dan Mocuta, Nadine Collaert

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017

Hybrid InGaAs/SiGe CMOS circuits with 2D and 3D monolithic integration.

V. Deshpande, Herwig Hahn, V. Djara, E. O'Connor, Daniele Caimi, Marilyne Sousa, Jean Fompeyrine, L. Czornomaz

Proceedings of the 47th European Solid-State Device Research Conference, 2017