V. Carl Hamacher

According to our database1, V. Carl Hamacher authored at least 38 papers between 1971 and 2007.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing.
Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007

2004
An effective analytical model for deflection routing in hierarchical ring interconnection networks.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004

2001
Hierarchical Ring Network Configuration and Performance Modeling.
IEEE Trans. Computers, 2001

1997
Performance and Configuration of Hierarchical Ring Networks for Multiprocessors.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1995
Design and Analysis of Hierarchical Ring Networks for Shared-Memory Multiprocessors.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

1994
Comparison of Mesh and Hierarchical Networks for Multiprocessors.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Response to "One-Bit Delay in Ring Networks".
IEEE Trans. Computers, 1993

1991
Analyzing Hard-Real-Time Programs For Guaranteed Schedulability.
IEEE Trans. Software Eng., 1991

A Hybrid Token/Insertion Ring LAN.
Proceedings of the Proceedings IEEE INFOCOM '91, 1991

1990
Utilizing Bandwidth Sharing in the Slotted Ring.
IEEE Trans. Computers, 1990

Computer organization, 3rd Edition.
McGraw-Hill computer science series, McGraw-Hill, ISBN: 978-0-07-025685-9, 1990

1989
On the Universality of Multipath Multistage Interconnection Networks.
J. Parallel Distributed Comput., 1989

Approximate Analysis of Non-Exhautive Multiserver Polling Systems with Applications to Local Area Networks.
Comput. Networks, 1989

1988
A unified modeling methodology for performance evaluation of distributed discrete event simulation mechanisms.
Proceedings of the 20th conference on Winter simulation, 1988

A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Semi-Static Dataflow.
Proceedings of the International Conference on Parallel Processing, 1988

1987
On the Permutation Capability of Multistage Interconnection Networks.
IEEE Trans. Computers, 1987

1986
Analysis of Digital Voice Communication Under Polling.
Proceedings of the IEEE International Conference on Communications: Integrating the World Through Communications, 1986

1985
Short-Packet Transfer Performance in Local Area Ring Networks.
IEEE Trans. Computers, 1985

Data Flow on a Queue Machine.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984
Short-Packet Transfer Performance in Local Area Rings.
Proceedings of the Proceedings IEEE INFOCOM 84, San Francisco, CA, USA, April 9-12, 1984, 1984

1983
CADAC: A Controlled-Precision Decimal Arithmetic Unit.
IEEE Trans. Computers, 1983

1982
Access Response on a Collision-Free Local Bus.
Comput. Networks, 1982

1981
Collision-Free Access Control for Computer Communication Bus Networks.
IEEE Trans. Software Eng., 1981

Collision-Free Local Area Bus Network Performance Analysis.
IBM J. Res. Dev., 1981

TORNET: A local area network.
Proceedings of the seventh symposium on Data communications, 1981

1980
Performance of a Collision-Free Local Bus Network Having Asynchronous Distributed Control.
Proceedings of the 7th Annual Symposium on Computer Architecture, 1980

1978
Hardware Support for the Concurrent Programming in Loosely Coupled Multiprocessors.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

1977
Low Level Architecture Features for Supporting Process Communication.
Comput. J., 1977

1976
Hardware Support for Inter-Process Communication and Processor Sharing.
Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976

1974
Pattern Synchronization in Two-Dimensional Cellular Spaces
Inf. Control., September, 1974

Authors' Reply.
IEEE Trans. Computers, 1974

B 74-28 Computer Hardware and Software: An Interdisciplinary Introduction.
IEEE Trans. Computers, 1974

On Relating Small Computer Performance to Design Parameters.
Proceedings of the 2nd Annual Symposium on Computer Architecture, 1974

1973
An Augmented Iterative Array for High-Speed Binary Division.
IEEE Trans. Computers, 1973

Design of a Fully Variable - Length Structured Minicomputer.
Proceedings of the 1st Annual Symposium on Computer Architecture, 1973

1972
Ternary logic in parallel multipliers.
Comput. J., 1972

1971
Machine Complexity Versus Interconnection Complexity in Iterative Arrays.
IEEE Trans. Computers, 1971


  Loading...