V. Bharath Sreenivasulu

Orcid: 0000-0003-3064-1522

According to our database1, V. Bharath Sreenivasulu authored at least 7 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications.
IEEE Access, 2024

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications.
IEEE Access, 2024

Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective.
IEEE Access, 2024

2023
Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications.
Microelectron. J., October, 2023

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison.
IEEE Access, 2023

2022
Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs.
Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

2021
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes.
Microelectron. J., 2021


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