Uwe Gläser

According to our database1, Uwe Gläser authored at least 21 papers between 1989 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1999
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Modell Evaluation Using Genetic Manipulation Techniques.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
The Impact of Area Optimization for the Power Consumption of Controllers.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits.
Proceedings of the Parallel Computing: Fundamentals, 1997

An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Automatic Test Pattern Generation with Optimal Load Balancing.
Proceedings of the Parallel Virtual Machine, 1996

An ATPG-Based Framework for Verifying Sequential Equivalence.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Improving topological ATPG with symbolic techniques.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

FOGBUSTER: an efficient algorithm for sequential test generation.
Proceedings of the Proceedings EURO-DAC'95, 1995

Systems Level Specification and Modeling of Reactive Systems: Concepts, Methods, and Tools.
Proceedings of the Computer Aided Systems Theory, 1995

Gate delay fault test generation for non-scan circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

Logic optimization by an improved sequential redundancy addition and removal techniques.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Mehrebenen-Testgenerierung für synchrone Schaltwerke.
PhD thesis, 1994

Testability Analysis for Test Generation in Synchronous Sequential Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Fault behavior and testability of asynchronous CMOS circuits.
Microprocess. Microprogramming, 1993

CMOS Bridges and Resistive Transistor Faults: I<sub>DDQ</sub> versus Delay Effects.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

MILEF: an efficient approach to mixed level automatic test pattern generation.
Proceedings of the conference on European design automation, 1992

1989
Fehlererkennung und Fehlertoleranz beim assoziativen RAM(ARAM)-Speicher.
Proceedings of the Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 1989


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