Urs Egger
According to our database1,
Urs Egger
authored at least 8 papers
between 2013 and 2022.
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Bibliography
2022
HERMES-Core - A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.
IEEE J. Solid State Circuits, 2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
2016
Controller architecture for low-latency access to phase-change memory in OpenPOWER systems.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2013
Proceedings of the 18th International Conference on Digital Signal Processing, 2013