Uppugunduru Anil Kumar

Orcid: 0000-0003-4328-6953

Affiliations:
  • BITS Pilani, Department of Electrical and Electronics Engineering, Hyderabad, India


According to our database1, Uppugunduru Anil Kumar authored at least 20 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks.
IEEE Access, 2024

Energy-Efficient Ternary Multiplier.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications.
IEEE Embed. Syst. Lett., September, 2023

Design methodology for highly accurate approximate multipliers for error resilient applications.
Comput. Electr. Eng., September, 2023

A General Methodology to Optimize Flagged Constant Addition.
J. Circuits Syst. Comput., January, 2023

Improved approximate multiplier architecture for image processing and neural network applications.
Microprocess. Microsystems, 2023

Power Efficient Approximate Ternary Subtractor for Image Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Low-Power Approximate Multiplier Architecture for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Low Power Approximate Divider and Square Root Circuits for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Design of Energy Efficient Posit Multiplier.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation.
Microprocess. Microsystems, October, 2022

A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications.
J. Circuits Syst. Comput., 2022

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module.
IEEE Embed. Syst. Lett., 2022

Compressor based hybrid approximate multiplier architectures with efficient error correction logic.
Comput. Electr. Eng., 2022

2021
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications.
IEEE Embed. Syst. Lett., 2021

Lower part OR based Approximate Multiplier for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Approximate Multiplier Architectures for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Power-Efficient MLOA for error resilient applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing.
Proceedings of the Machine Learning, Image Processing, Network Security and Data Sciences, 2020


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