Un-Ku Moon

IEEE J. Solid State Circuits, December, 2023

PLL-SAR: A New High-Speed Analog to Digital Converter Architecture.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC.

[BibT_eX]

[DOI]

Hang Hu

Vladimir Veselý

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Passive Third Order Continuous-Time ΔΣ Modulator with Q Enhancement Technique.

[BibT_eX]

[DOI]

Hang Hu

Vladimir Veselý

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Switched-Capacitor Circuits.

[BibT_eX]

[DOI]

David J. Allstot

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Low-Distortion Correlated Level Shifting Sample-and-Hold Stage.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

2020

A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits.

[BibT_eX]

[DOI]

Tao He

Manjunath Kareppagoudr

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Cascoded Ring Amplifiers for High Speed and High Accuracy Settling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL.

[BibT_eX]

[DOI]

Hang Hu

Bohui Xiao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Calvin Y. Lee

Mohamed Dessouky

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier.

[BibT_eX]

[DOI]

Bohui Xiao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

An Oversampling Stochastic ADC Using VCO-Based Quantizers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Session 14 overview: High-resolution ADCs: Data converter subcommittee.

[BibT_eX]

[DOI]

Matt Straayer

Seung-Tak Ryu

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Session 22 overview: Gigahertz data converters: Data converter subcommittee.

[BibT_eX]

[DOI]

Kostas Doris

Jan Westra

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Power Optimized Comparator Selecting Method For Stochastic ADC.

[BibT_eX]

[DOI]

Bohui Xiao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Power Efficient SAR Algorithm for High Resolution ADCs.

[BibT_eX]

[DOI]

Calvin Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Pseudo-pseudo-differential circuits.

[BibT_eX]

[DOI]

Tao He

Manjunath Kareppagoudr

Yi Zhang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Session 16 overview: Gigahertz data converters.

[BibT_eX]

[DOI]

Jan Mulder

Paul Ferguson

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 28 overview: Hybrid ADCs.

[BibT_eX]

[DOI]

Tai-Cheng Lee

Bob Verbruggen

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A highly compact wideband continuous-time transimpedance low-pass filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Voltage domain correction technique for timing skew errors in time interleaved ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multi-path ring amplifier with dynamic biasing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Data converter reflections: 19 papers from the last ten years that deserve a second look.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation.

[BibT_eX]

[DOI]

Yue Hu

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Practical modeling of comparator metastability for conventional and LSB-first SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

MDLL/PLL dual-path clock generator.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A ΔΣ ADC using an LSB-first SAR quantizer.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Selectable starting bit SAR ADC.

[BibT_eX]

[DOI]

Jerry Leung

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A single OpAmp 2nd-Order ΔΣ ADC with a double integrating quantizer.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of metastability errors in asynchronous SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A VCO-based spatial averaging stochastic ADC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling.

[BibT_eX]

[DOI]

Ho-Young Lee

IEEE J. Solid State Circuits, 2014

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Stochastic approximation register ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Time amplifiers based on phase accumulation.

[BibT_eX]

[DOI]

Yue Hu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

LSB-first SAR ADC with bit-repeating for reduced energy consumption.

[BibT_eX]

[DOI]

Jerry Leung

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Analysis and performance trade-offs of linearity calibration for stochastic ADCs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Resistive correction of low output impedance high-speed current-steering DACs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Emerging analog-to-digital converters.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2014, 2014

Inherently linear time symmetric pulse width modulation.

[BibT_eX]

[DOI]

Yue Hu

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 2013

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End.

[BibT_eX]

[DOI]

Omid Rajaee

IEEE J. Solid State Circuits, 2013

Message From the Outgoing Editor-in-Chief.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Analysis of back-end flash in a 1.5b/stage pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Parallel gain enhancement technique for switched-capacitor circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Blind background calibration of harmonic distortion based on selective sampling.

[BibT_eX]

[DOI]

Ho-Young Lee

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

New Associate Editor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

New Associate Editors.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

Ring Amplifiers for Switched Capacitor Circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 10-b Ternary SAR ADC With Quantization Time Information Utilization.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.

[BibT_eX]

[DOI]

Terri S. Fiez

Proceedings of the 25th International Conference on VLSI Design, 2012

A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

A 71dB dynamic range third-order ΔΣ TDC using charge-pump.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

Little-known features of well-known creatures.

[BibT_eX]

[DOI]

Shanthi Pavan

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS.

[BibT_eX]

[DOI]

Ho-Young Lee

Bumha Lee

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Correlated jitter sampling for jitter cancellation in pipelined TDC.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

The effect of correlated level shifting on noise performance in switched capacitor circuits.

[BibT_eX]

[DOI]

Tawfiq Musah

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Domino-Logic-Based ADC for Digital Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Design-Oriented Analysis of Circuits With Equality Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Analysis of Residue Integration Sampling With Improved Jitter Immunity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Binary Access Memory: An optimized lookup table for successive approximation applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 10b Ternary SAR ADC with decision time quantization based redundancy.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Stochastic Flash Analog-to-Digital Conversion.

[BibT_eX]

[DOI]

Peter Kurahashi

Daniel Knierim

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS.

[BibT_eX]

[DOI]

Charles T. Peach

David J. Allstot

IEEE J. Solid State Circuits, 2010

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

Continuous-Time Input Pipeline ADCs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

An interstage correlated double sampling technique for switched-capacitor gain stages.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Pseudo-differential zero-crossing-based circuit with differential error suppression.

[BibT_eX]

[DOI]

Tawfiq Musah

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A double-sampled path-coupled single-loop ΣΔ modulator using noise-shaped integrating quantizer.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

PDF folding for stochastic flash ADCs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Asynchronous CLS for Zero Crossing based Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Digital PLL With a Stochastic Time-to-Digital Converter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Introducing Jump-Start Tutorials.

[BibT_eX]

[DOI]

Anthony Chan Carusone

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Guest Editorial Special Issue on ISCAS 2008.

[BibT_eX]

[DOI]

Anthony Chan Carusone

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Automated Design and Optimization of Low-Noise Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme.

[BibT_eX]

[DOI]

Min-Gyu Kim

IEEE J. Solid State Circuits, 2009

A multiplexer-based digital passive linear counter (PLINCO).

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.

[BibT_eX]

[DOI]

Tawfiq Musah

Hasnain Lakdawala

Krishnamurthy Soumyanath

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A continuous-time input pipeline ADC with inherent anti-alias filtering.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A Note From the Editors.

[BibT_eX]

[DOI]

Gianluca Setti

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Sensitivity Analysis for Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A Wide-Tracking Range Clock and Data Recovery Circuit.

[BibT_eX]

[DOI]

Gu-Yeon Wei

IEEE J. Solid State Circuits, 2008

A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Parameter variation analysis for voltage controlled oscillators in phase-locked loops.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer.

[BibT_eX]

[DOI]

Omid Rajaee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Multi-loop efficient sturdy MASH delta-sigma modulators.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Reducing the effects of component mismatch by using relative size information.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Periodic Steady-State Analysis Augmented with Design Equality Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Noise tolerant oscillator design using perturbation projection vector analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 1V downconversion filter using duty-cycle controlled bandwidth tuning.

[BibT_eX]

[DOI]

Peter Kurahashi

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A continuous-time input pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Sub 1-V Constant Gm- C Switched-Capacitor Current Source.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.

[BibT_eX]

[DOI]

Ting Wu

Kartikeya Mayaram

IEEE J. Solid State Circuits, 2007

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Mixed-Order Sturdy MASH Delta-Sigma Modulator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Considerations for Stochastic Analog-to-Digital Conversion.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Time-Shifted CDS Enhancement of Comparator-Based MDAC for Pipelined ADC Applications.

[BibT_eX]

[DOI]

Omid Rajaee

Proceedings of the 14th IEEE International Conference on Electronics, 2007

State-of-the-art continuous-time filters from scratch.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Efficient Design Procedure for High-Speed Low-Power Dual-Modulus CMOS Prescalers.

[BibT_eX]

[DOI]

Ranganathan Desikachari

Mark Steeds

Jeffrey M. Huard

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Digitally-Enhanced Phase-Locking Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance.

[BibT_eX]

[DOI]

Merrick Brownlee

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 1V 10b 30MSPS Switched-RC Pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Dependence of LC VCO oscillation frequency on bias current.

[BibT_eX]

[DOI]

Ting Wu

Kartikeya Mayaram

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Constant transconductance bias circuit with an on-chip resistor.

[BibT_eX]

[DOI]

Nasser Talebbeydokhti

Peter Kurahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The effect of switch resistance on pipelined ADC MDAC settling time.

[BibT_eX]

[DOI]

Josh Carnes

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.6V Highly Linear Switched-R-MOSFET-C Filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 1.6Gbps Digital Clock and Data Recovery Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

A low-Voltage 10-bit CMOS DAC in 0.01-mm2 die area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters.

[BibT_eX]

[DOI]

Gil-Cho Ahn

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A 0.8-V accurately tuned linear continuous-time filter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Noise-shaping techniques applied to switched-capacitor voltage regulators.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A generic multilevel multiplying D/A converter for pipelined ADCs.

[BibT_eX]

[DOI]

Vivek Sharma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 10-bit algorithmic A/D converter for cytosensor application.

[BibT_eX]

[DOI]

Thirumalai Rengachari

Vivek Sharma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of supply and ground noise sensitivity in ring and LC oscillators.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low spur fractional-N frequency synthesizer architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Will continued process-node shrinks kill high-performance analog design?

[BibT_eX]

[DOI]

Hisashi (Sam) Shichijo

Albert Z. Wang

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Continuous-time filter design optimized for reduced die area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems.

[BibT_eX]

[DOI]

Gang Huang

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Analysis of charge-pump phase-locked loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-distortion delta-sigma topologies for MASH architectures.

[BibT_eX]

[DOI]

José B. Silva

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An improved algorithmic ADC clocking scheme.

[BibT_eX]

[DOI]

Min-Gyu Kim

Gil-Cho Ahn

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Jitter in high-speed serial and parallel links.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A 0.8V accurately-tuned continuous-time filter.

[BibT_eX]

[DOI]

Gowtham Vemulapalli

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Background calibration techniques for multistage pipelined ADCs with digital redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Analysis of PLL clock jitter in high-speed serial links.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Continuous-time, frequency translating, bandpass delta-sigma modulator.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An extended radix-based digital calibration technique for multi-stage ADC.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation.

[BibT_eX]

[DOI]

Tetsuya Kajita

VLSI Design, 2002

A two-chip interface for a MEMS accelerometer.

[BibT_eX]

[DOI]

Tetsuya Kajita

IEEE Trans. Instrum. Meas., 2002

A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps.

[BibT_eX]

[DOI]

Mustafa Keskin

IEEE J. Solid State Circuits, 2002

Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

High-speed pipelined A/D converter using time-shifted CDS technique.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS.

[BibT_eX]

[DOI]

David A. Yokoyama-Martin

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

Digital techniques for improved ΔΣ data conversion.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

Low-voltage pipelined ADC using opamp-reset switching technique.

[BibT_eX]

[DOI]

Lei Wu

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Area efficient CMOS charge pump circuits.

[BibT_eX]

[DOI]

Ryan Perigny

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multibit Sigma-Delta ADC with mixed-mode DAC error correction.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator.

[BibT_eX]

[DOI]

Mustafa Keskin

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2.

[BibT_eX]

[DOI]

Brandon Greenley

Raymond Veith

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A CMOS self-calibrating frequency synthesizer.

[BibT_eX]

[DOI]

William B. Wilson

Kadaba R. Lakshmikumar

Liang Dai

IEEE J. Solid State Circuits, 2000

Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

CMOS high-frequency switched-capacitor filters for telecommunication applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

Efficient error-cancelling algorithmic ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A switched-capacitor DAC with analog mismatch correction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An adaptive offset cancellation mixer for direct conversion receivers in 2.4 GHz CMOS.

[BibT_eX]

[DOI]

Mark Lehne

John T. Stonick

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Improved adaptive digital compensation for cascaded ΔΣ ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Digital techniques for improving the accuracy of data converters.

[BibT_eX]

[DOI]

Jesper Steensgaard

IEEE Commun. Mag., 1999

Capacitor mismatch error cancellation technique for a successive approximation A/D converter.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mismatch-shaping serial digital-to-analog converter.

[BibT_eX]

[DOI]

Jesper Steensgaard

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-voltage switched-capacitor circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1993

Low-distortion Continuous-time R-MOSFET-C Filters.

[BibT_eX]