Uming Ko
According to our database1,
Uming Ko
authored at least 27 papers
between 1985 and 2017.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For leadership in ultra-low power circuit techniques".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
IEEE J. Solid State Circuits, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors.
Proc. IEEE, 2010
2008
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Solutions for logic and processor core design at the 45nm technology node & and below.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the 42nd Design Automation Conference, 2005
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
1997
Hybrid dual-threshold design techniques for high-performance processors with low-power features.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995
1985
Contactless VLSI Laser Probing.
Proceedings of the Proceedings International Test Conference 1985, 1985