Umesh Nawathe

According to our database, Umesh Nawathe authored at least 5 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of two.

2014

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.

Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

IEEE J. Solid State Circuits, 2014

2013

3.6GHz 16-core SPARC SoC processor in 28nm.

Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2008

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.

Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, David Greenhill

IEEE J. Solid State Circuits, 2008

2007

An 8-Core 64-Thread 64b Power-Efficient SPARC SoC.

Umesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King C. Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2).

Timothy Johnson, Umesh Nawathe

Proceedings of the 2007 International Symposium on Physical Design, 2007