Umar Afzaal

According to our database, Umar Afzaal authored at least 9 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

On the Evolutionary Synthesis of Fault-Resilient Digital Circuits.

Umar Afzaal, Abdus Sami Hassan, Muhammad Usman, Jeong-A Lee

IEEE Trans. Evol. Comput., April, 2023

Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction.

Byungho Choi, Yonghwi Kwon, Umar Afzaal, Youngsoo Shin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020

Improved error detection performance of logic implication checking in FPGA circuits.

Umar Afzaal, Abdus Sami Hassan, Jeong-A Lee

Microprocess. Microsystems, 2020

Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems.

Umar Afzaal, Jeong-A Lee

Proceedings of the International Conference on Information and Communication Technology Convergence, 2020

Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation.

Umar Afzaal, Jeong-A Lee

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates.

Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA.

Inayat Ullah, Umar Afzaal, Zahid Ullah, Jeong-A Lee

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking.

Umar Afzaal, Abdus Sami Hassan, Tooba Arifeen, Jeong-A Lee

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

FPGA-based design of a self-checking TMR voter.

Umar Afzaal, Jeong-A Lee

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017