Ulrike Pfannkuchen

According to our database, Ulrike Pfannkuchen authored at least 7 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

IJTAG Through a Two-Pin Chip Interface.

Manu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-François Côté, Givargis Danialy, Martin Keim, Lori Schramm

Proceedings of the IEEE International Test Conference, 2020

2018

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

On enabling diagnosis for 1-Pin Test fails in an industrial flow.

Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

A lightweight X-masking scheme for IoT designs.

Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen

Proceedings of the International Test Conference in Asia, 2017

Machine learning based test pattern analysis for localizing critical power activity areas.

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

Automated Optimization of Scan Chain Structure for Test Compression-Based Designs.

Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014

Automated formal verification of X propagation with respect to testability issues.

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß

Proceedings of the 9th International Design and Test Symposium, 2014