Ulrich Ramacher

According to our database1, Ulrich Ramacher authored at least 34 papers between 1989 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
Architecture and implementation of a Software-Defined Radio baseband processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007
Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Des. Test Comput., 2007

Software-Defined Radio Prospects for Multistandard Mobile Phones.
Computer, 2007

Challenges and prospects of SDR for mobile phones.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
Image Segmentation by Networks of Spiking Neurons.
Neural Comput., 2005

3D Chip Stack Technology Using Through-Chip Interconnects.
IEEE Des. Test Comput., 2005

Automatic speech recognition with neural spike trains.
Proceedings of the 9th European Conference on Speech Communication and Technology, 2005

Temporal Sound Processing by Cochlear Nucleus Octopus Neurons.
Proceedings of the Artificial Neural Networks: Biological Inspirations, 2005

Embedded vision platform for video surveillance systems.
Proceedings of the Electronic Imaging: Image and Video Communications and Processing 2005, 2005

Wireless platforms: GOPS for cents and MilliWatts.
Proceedings of the 42nd Design Automation Conference, 2005

2004
A low-power memory hierarchy for a fully programmable baseband processor.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation.
Proceedings of the Image Processing: Algorithms and Systems III, 2004

Pulse coupled neural networks with adaptive synapses for image segmentation.
Proceedings of the ARCS 2004, 2004

2003
100 GOPS vision processor for automotive applications.
SIGARCH Comput. Archit. News, 2003

A 100-GOPS Programmable Processor for Vehicle Vision Systems.
IEEE Des. Test Comput., 2003

Correlation-based feature detection using pulsed neural networks.
Proceedings of the NNSP 2003, 2003

A programmable platform for software-defined radio.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity.
Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing, 2002

Application Specific Embedded Processors for Next Generation Communication Systems.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.
Proceedings of the Artificial Neural Networks, 2002

2001
Crosstalk noise in future digital CMOS circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1999
Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik.
Proceedings of the PEARL 99: Multimedia und Automatisierung, 1999

1996
SEE-1 - A Vision System for Use in Real World Environments.
Proceedings of the Artificial Neural Networks, 1996

1995
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system.
Proceedings of IPPS '95, 1995

1993
A general-purpose signal processor architecture for neurocomputing and preprocessing applications.
J. VLSI Signal Process., 1993

Hamiltonian dynamics of neural networks.
Neural Networks, 1993

Design of a general-purpose neural signal processor.
Neurocomputing, 1993

Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips.
Int. J. Neural Syst., 1993

Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1.
Int. J. Neural Syst., 1993

Architecture and VLSI Design of a VLSI Neural Signal Processor.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine.
J. Parallel Distributed Comput., 1992

Mikroelektronische Realisierung von künstlichen neuronalen Netzen / Microelectronic Realizations of artificial neural networks.
it Inf. Technol., 1992

1990
Fine-grain system architectures for systolic emulation of neural algorithms.
Proceedings of the Application Specific Array Processors, 1990

1989
Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area.
Proceedings of the Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 1989


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