Ulrich Nageldinger

According to our database, Ulrich Nageldinger authored at least 25 papers between 1996 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited).

Jochen Zimmermann, Oliver Bringmann, Joachim Gerlach, Florian Schaefer, Ulrich Nageldinger

Proceedings of the Forum on specification and Design Languages, 2008

Generating MARTE Allocation Models from Activity Threads.

Andreas W. Liehr, Heike S. Rolfs, Klaus Buchenrieder, Ulrich Nageldinger

Proceedings of the Forum on specification and Design Languages, 2008

Generation of MARTE Allocation Models from Activity Threads.

Andreas W. Liehr, Klaus J. Buchenrieder, Heike S. Rolfs, Ulrich Nageldinger

Proceedings of the Languages for Embedded Systems and their Applications, 2008

2005

A Low-Cost Realization of an Adaptable Protocol Processing Unit.

Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Reducing the Power Consumption of FPGAs through Retiming.

Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger

Proceedings of the 12th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2005), 2005

2002

System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model.

Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Integration of Reconfigurable Hardware into System-Level Design.

Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Coarse-grained reconfigurable architecture design space exploration.

Ulrich Nageldinger

ISBN: 978-3-925178-65-8, 2001

2000

Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.

Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Integrated Circuit Design, 2000

Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 2000

Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract).

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of ASP-DAC 2000, 2000

1999

Interfacing the MoM-PDA to an Internet-based Development System.

Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber

Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

XMDS: The Xputer Multimedia Development System.

Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber

Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

An Internet Based Development Framework for Reconfigurable Computing.

Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Mapping Applications onto Reconfigurable Kress Arrays.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998

On Reconfigurable Co-processing Units.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 1998

Parallelization in Co-Compilation for Configurable Accelerators.

Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger

Proceedings of the ASP-DAC '98, 1998

1997

An operating system for custom computing machines based on the Xputer paradigm.

Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Data scheduling to increase performance of parallel accelerators.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

A Novel Sequencer Hardware for Application Specific Computing.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

A Novel Universal Sequencer Hardware.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the Architektur von Rechensystemen, Arbeitsteilige Systemarchitekturen: Konzepte, Lösungen, Anwendungen, Trends, 1997

1996

A Partitioning Programming Environment for a Novel Parallel Architecture.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of IPPS '96, 1996

A Synthesis System For Bus-Based Wavefront Array Architectures.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996