Ulrich Langmann

According to our database, Ulrich Langmann authored at least 24 papers between 1988 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output.

Christopher Weyers, Pierre Mayr, Johannes W. Kunze, Ulrich Langmann

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 90GHz 65nm CMOS Injection-Locked Frequency Divider.

Pierre Mayr, Christopher Weyers, Ulrich Langmann

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system.

Marcus Schämann, Sebastian Hessel, Ulrich Langmann, Martin Bücker

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery.

Thomas Suttorp, Ulrich Langmann

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Channel Equalization in HSDPA Receivers: Trade-Off between Performance and Complexity with a Variable Oversampling.

Marcus Schämann, Martin Bücker, Sebastian Hessel, Ulrich Langmann

Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

2005

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator.

Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff

IEEE J. Solid State Circuits, 2005

2003

Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators.

Frank Henkel, Ulrich Langmann

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator.

Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers.

Frank Henkel, Ulrich Langmann, André Hanke, Stefan Heinen, Elmar Wagner

IEEE J. Solid State Circuits, 2002

2000

A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications.

Günter Grau, Ulrich Langmann, Wolfgang Winkler, Dieter Knoll, Jörg Osten, Klaus Pressel

IEEE J. Solid State Circuits, 2000

A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver.

Tobias Ellermeyer, Ulrich Langmann, Berthold Wedding, Wolfgang Pöhlmann

IEEE J. Solid State Circuits, 2000

1999

A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems.

Johann-Christoph Scheytt, Gerhard Hanke, Ulrich Langmann

IEEE J. Solid State Circuits, 1999

Design of high speed bipolar Si/SiGe ICs for optical wide band communications.

Thorsten Baumheinrich, Ulrich Langmann

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A 10-Gb/s silicon bipolar IC for PRBS testing.

Oliver Kromat, Ulrich Langmann, Gerhard Hanke, William J. Hillery

IEEE J. Solid State Circuits, 1998

1997

A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC.

Thorsten Baumheinrich, Bernd Prégardier, Ulrich Langmann

IEEE J. Solid State Circuits, 1997

1996

A 1.2-GS/s 8-b silicon bipolar track & hold IC.

Bernd Prégardier, Ulrich Langmann, William J. Hillery

IEEE J. Solid State Circuits, 1996

Si bipolar 14 Gb/s 1: 4-demultiplexer IC for system applications.

Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin

IEEE J. Solid State Circuits, 1996

Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC.

Zhihao Lao, Ulrich Langmann

IEEE J. Solid State Circuits, 1996

1995

A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems.

Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin

IEEE J. Solid State Circuits, February, 1995

1994

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC.

Ansgar Pottbacker, Ulrich Langmann

IEEE J. Solid State Circuits, December, 1994

1993

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s.

Matthias Bussmann, Ulrich Langmann, Wiliam J. Hillery, Wiliam W. Brown

IEEE J. Solid State Circuits, December, 1993

1992

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s.

Ansgar Pottbacker, Ulrich Langmann, Hans-Ulrich Schreiber

IEEE J. Solid State Circuits, December, 1992

1991

Multi-Gb/s Silicon Bipolar Clock Recovery IC.

Zhigong Wang, Ulrich Langmann, Berthold G. Bosch

IEEE J. Sel. Areas Commun., 1991

1988

A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter.

Detlef Daniel, Ulrich Langmann, Berthold G. Bosch

IEEE J. Solid State Circuits, June, 1988