We stand with Ukraine

We stand with Ukraine

Ulrich Golze

According to our database¹, Ulrich Golze authored at least 17 papers between 1975 and 2012.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

1975

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1985

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1995

2000

2005

2010

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Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2012

25 Jahre Entwurf integrierter Schaltungen.

[BibT_eX]

[DOI]

Proceedings of the 40 Jahre Informatik an der Technischen Universität Braunschweig, 1972, 2012

2004

Lightweight Firm Real-Time Extensions for Low Memory Profile Java Systems.

[BibT_eX]

[DOI]

,

Proceedings of the On the Move to Meaningful Internet Systems 2004: OTM 2004 Workshops: OTM Confederated International Workshops and Posters, 2004

2003

An Improved Intermediate Representation for Datapath Generation.

[BibT_eX]

,

,

,

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2001

Efficient Production of Computer-Based Training in Chip Desig.

[BibT_eX]

[DOI]

Tamer Çatalkaya

,

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

1998

Entwurf von Controller-Schaltungen für Kommunikationsprotokolle mit dem Protocol-Compiler von Synopsys.

[BibT_eX]

,

,

Ulrich Holtmann

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998

Entwicklung multimedialer Lernprogramme im Chip-Entwurf für und als Teil der Lehre.

[BibT_eX]

Tamer Çatalkaya

,

Proceedings of the Tagungsband zum Workshop "Multimedia-Systeme" im Rahmen der GI-Jahrestagung 1998. Magdeburg, 1998

1996

VLSI chip design with the hardware description language VERILOG - an introduction based on a large RISC processor design.

[BibT_eX]

Springer, ISBN: 978-3-540-60032-9, 1996

1995

VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL.

[BibT_eX]

Lehrbuch Informatik, Vieweg, ISBN: 978-3-528-05416-8, 1995

Der RISC-Prozessor TOOBSIE - Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten.

[BibT_eX]

Vieweg, ISBN: 978-3-528-05417-5, 1995

1988

RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification.

[BibT_eX]

[DOI]

,

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986

Ein Public-Key-Code Kryptographie-Prozessor.

[BibT_eX]

[DOI]

,

it Inf. Technol., 1986

Ein hierarchischer inkrementeller Designrulechecker.

[BibT_eX]

[DOI]

Jürgen Hannken-Illjes

,

it Inf. Technol., 1986

1982

Petri Net Implementations by a Universal Cell Space

[BibT_eX]

[DOI]

,

Inf. Control., 1982

1981

Recursive Paths in Cross-Connected Trees and an Application to Cell Spaces.

[BibT_eX]

[DOI]

Hans Georg Carstens

,

Math. Syst. Theory, 1981

1979

Lokale und globale Synchronisation.

[BibT_eX]

J. Inf. Process. Cybern., 1979

1978

(A-)Synchronous (Non-)Deterministic Cell Spaces Simulating Each Other.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 1978

1975

Differences between 1- and 2-Dimensional Cell Spaces.

[BibT_eX]

Proceedings of the Automata, Languages, Development: At the crossroads of biology, mathematics and computer science, result of an international conference held at Noordwijkerhout, The Netherlands, March 31, 1975

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