Ulrich Brüning

Affiliations:
  • University of Heidelberg, Institute of Computer Engineering, Heidelberg, Germany
  • Technical University of Berlin, Germany (PhD 1987)


According to our database1, Ulrich Brüning authored at least 39 papers between 1987 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2021
BrainScaleS Large Scale Spike Communication using Extoll.
CoRR, 2021

2019
Development of a RISC-V-Conform Fused Multiply-Add Floating-Point Unit.
Supercomput. Front. Innov., 2019

2017
Automatic and Transparent Resource Contention Mitigation for Improving Large-Scale Parallel File System Performance.
Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

2016
Using Balanced Data Placement to Address I/O Contention in Production Environments.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
openHMC - a configurable open-source hybrid memory cube controller.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Communication Models for Distributed Intel Xeon Phi Coprocessors.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

Scalable communication architecture for network-attached accelerators.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2013
On Achieving High Message Rates.
Proceedings of the 13th IEEE/ACM International Symposium on Cluster, 2013

2012
MPI Functions and Their Impact on Interconnect Hardware.
Proceedings of the Recent Advances in the Message Passing Interface, 2012

2011
Introduction.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
High Performance Networks.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect.
Proceedings of the 2010 IEEE International Conference on Cluster Computing, 2010

2009
An FPGA-Based Custom High Performance Interconnection Network.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication.
Proceedings of the ICPP 2009, 2009

Efficient Virtualization of High-Performance Network Interfaces.
Proceedings of the Eighth International Conference on Networks, 2009

An FPGA based verification platform for HyperTransport 3.x.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A HyperTransport 3 Physical Layer Interface for FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
An open-source HyperTransport core.
ACM Trans. Reconfigurable Technol. Syst., 2008

VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007
A versatile, low latency HyperTransport core.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2005
Swordfish: A Simulator for High-Performance Networks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Performance Evaluation of the ATOLL Interconnect.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

2004
High performance cluster computing with 3-D nonlinear diffusion filters.
Real Time Imaging, 2004

Future Building Blocks for Parallel Architectures.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

2003
Systeme für eine hocheffiziente elektrische und optische Kurzstreckenübertragung im SAN-Bereich (Systems for High-Efficient Electrical and Optical Short-Distance Data Transmission in System-Area-Networks).
it Inf. Technol., 2003

SEED2002 Support of Educational course for Electronic Design.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Low Level Parallelization of Nonlinear Diffusion Filtering Algorithms for Cluster Computing Environments.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
ATOLL: Performance and Cost Optimization of a San Interconnect.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Designing 3-D Nonlinear Diffusion Filters for High Performance Cluster Computing.
Proceedings of the Pattern Recognition, 2002

2000
ATOLL, a New Switched, High Speed Interconnect in Comparison to Myrinet and SCI.
Proceedings of the Parallel and Distributed Processing, 2000

Cluster SMP Nodes with the ATOLL Network: A Look into the Future of System Area Networks.
Proceedings of the High-Performance Computing and Networking, 8th International Conference, 2000

1999
Trends und Entwicklungen der Kommunikationstechnik für den Aufbau von Rechnerclustern.
Prax. Inf.verarb. Kommun., 1999

ATOLL: A Network on a Chip.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1997
ATOLL: A High-Performance Communication Device for Massively Parallel Systems.
Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997

1996
MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

1994
Latency Hiding in Message-Passing Architectures.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1991
The Architecture of the European MIMD Supercomputer GENESIS.
Proceedings of the Distributed Memory Computing, 2nd European Conference, 1991

1987
Realisierungsprinzipien von Mikrorechnern hoher numerischer Leistung.
PhD thesis, 1987


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