Ulrich Brenner

According to our database, Ulrich Brenner authored at least 22 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Delay-Optimum Adder Circuits with Linear Size.

Ulrich Brenner, Benjamin David Görg

CoRR, 2024

Faster Linear-Size And-Or Path and Adder Circuits.

Ulrich Brenner, Anna Silvanus

CoRR, 2024

Bounds on soft rectangle packing ratios.

Judith Brecklinghaus, Ulrich Brenner, Oliver Kiss

Comput. Geom., 2024

2023

BonnLogic: Delay optimization by And-Or Path restructuring.

Ulrich Brenner, Anna Silvanus

Integr., March, 2023

2022

Constructing depth-optimum circuits for adders and And-Or paths.

Ulrich Brenner, Anna Silvanus, Jannik Silvanus

Discret. Appl. Math., 2022

Delay Optimization of Combinational Logic by AND-OR Path Restructuring.

Ulrich Brenner, Anna Silvanus

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2019

Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times.

Ulrich Brenner, Anna Hermann

ACM Trans. Algorithms, 2019

2018

<i>γ</i>-Soft packings of rectangles.

Ulrich Brenner

Comput. Geom., 2018

2017

Faster Adder Circuits for Inputs with Prescribed Arrival Times.

Ulrich Brenner, Anna Hermann

CoRR, 2017

2015

BonnPlace: A Self-Stabilizing Placement Framework.

Ulrich Brenner, Anna Hermann, Nils Hoppmann, Philipp Ochsendorf

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2013

BonnPlace Legalization: Minimizing Movement by Iterative Augmentation.

Ulrich Brenner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012

VLSI legalization with minimum perturbation by iterative augmentation.

Ulrich Brenner

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2008

Analytical Methods in Placement.

Ulrich Brenner, Jens Vygen

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms.

Ulrich Brenner, Markus Struzyna, Jens Vygen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A faster polynomial algorithm for the unbalanced Hitchcock transportation problem.

Ulrich Brenner

Oper. Res. Lett., 2008

2006

Theory and Practice of VLSI Placement

Ulrich Brenner

PhD thesis, 2006

2005

Faster and better global placement by a new transportation algorithm.

Ulrich Brenner, Markus Struzyna

Proceedings of the 42nd Design Automation Conference, 2005

2004

Legalizing a placement with minimum total movement.

Ulrich Brenner, Jens Vygen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Almost optimum placement legalization by minimum cost flow and dynamic programming.

Ulrich Brenner, Anna Pauli, Jens Vygen

Proceedings of the 2004 International Symposium on Physical Design, 2004

2003

An effective congestion-driven placement framework.

Ulrich Brenner, André Rohe

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001

Worst-case ratios of networks in the rectilinear plane.

Ulrich Brenner, Jens Vygen

Networks, 2001

2000

Faster Optimal Single-Row Placement with Fixed Ordering.

Ulrich Brenner, Jens Vygen

Proceedings of the 2000 Design, 2000