Ugo Mureddu

Orcid: 0000-0002-2216-6496

According to our database¹, Ugo Mureddu authored at least 9 papers between 2016 and 2022.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2022

An Evaluation Procedure for Comparing Clock Jitter Measurement Methods.

[BibT_eX]

[DOI]

Arturo Mollinedo Garay

Proceedings of the Smart Card Research and Advanced Applications, 2022

2019

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Transient Effect Ring Oscillators Leak Too.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

2018

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Optimization of the PLL based TRNG design using the genetic algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A comprehensive hardware/software infrastructure for IP cores design protection.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

Complete activation scheme for FPGA-oriented IP cores design protection.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Ugo Mureddu

Timeline

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