Uday Padmanabhan

According to our database, Uday Padmanabhan authored at least 4 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Robust Clock Tree Routing in the Presence of Process Variations.

Uday Padmanabhan, Janet Meiling Wang, Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Simulation and Design of Nanocircuits With Resonant Tunneling Devices.

Janet Meiling Wang, Bharat Sukhwani, Uday Padmanabhan, Dongsheng Ma, Kartik Sinha

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006

Statistical clock tree routing for robustness to process variations.

Uday Padmanabhan, Janet Meiling Wang, Jiang Hu

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design.

Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang

Proceedings of the 2005 Design, 2005