Uday Mallappa

According to our database, Uday Mallappa authored at least 15 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing.

Haichao Yang, Chang Eun Song, Weihong Xu, Behnam Khaleghi, Uday Mallappa, Monil Shah, Keming Fan, Mingu Kang, Tajana Rosing

CoRR, 2024

PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints.

Hesham Mostafa, Uday Mallappa, Mikhail Galkin, Mariano Phielipp, Somdeb Majumdar

CoRR, 2024

FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SoCs.

Uday Mallappa, Hesham Mostafa, Michael Galkin, Mariano Phielipp, Somdeb Majumdar

CoRR, 2024

2023

DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.

Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa

ACM Trans. Design Autom. Electr. Syst., July, 2023

2022

AI for Design Optimization and Design for AI Acceleration

Uday Mallappa

PhD thesis, 2022

Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.

Uday Mallappa, Chung-Kuan Cheng, Bill Lin

IEEE Embed. Syst. Lett., 2022

JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.

Uday Mallappa, Chung-Kuan Cheng, Bill Lin

IEEE Des. Test, 2022

TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks.

Uday Mallappa, Pranav Gangwar, Behnam Khaleghi, Haichao Yang, Tajana Rosing

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization.

Uday Mallappa, Sreedhar Pratty, David Brown

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PatterNet: explore and exploit filter patterns for efficient deep neural networks.

Behnam Khaleghi, Uday Mallappa, Duygu Yaldiz, Haichao Yang, Monil Shah, Jaeyoung Kang, Tajana Rosing

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

GRA-LPO: Graph Convolution Based Leakage Power Optimization.

Uday Mallappa, Chung-Kuan Cheng

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.

Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design.

Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul, Shangyuan Tong

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.

Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis.

Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul

Proceedings of the 36th IEEE International Conference on Computer Design, 2018