Uday A. Korat

Orcid: 0000-0001-6072-6506

According to our database1, Uday A. Korat authored at least 2 papers between 2017 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Reconfigurable Hardware Architecture for Principal Component Analysis.
Circuits Syst. Signal Process., 2019

2017
An efficient hardware implementation of vector-based odd-even merge sorting.
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017


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