Tzu-Chien Hsueh
Orcid: 0000-0002-8596-6976
According to our database1,
Tzu-Chien Hsueh
authored at least 17 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
CoRR, 2024
Monolithic Silicon-Photonics Linear-Algebra Accelerators Enabling Next-Gen Massive MIMO.
CoRR, 2024
2023
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
ChatGPT at the Speed of Light: Optical Comb-Based Monolithic Photonic-Electronic Linear-Algebra Accelerators.
CoRR, 2023
2022
Random Sampling-and-Averaging Techniques for Single-Photon Arrival-Time Detections in Quantum Applications: Theoretical Analysis and Realization Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2019
IEEE J. Solid State Circuits, 2019
2015
An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements.
IEEE J. Solid State Circuits, 2015
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR.
Proceedings of the Symposium on VLSI Circuits, 2015
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2010
A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation.
IEEE J. Solid State Circuits, 2010
A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009