Tzu-An Wei

According to our database, Tzu-An Wei authored at least 5 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS.

Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer.

Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Tsung-Hsien Lin

IEEE J. Solid State Circuits, 2016

2015

A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer.

Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin

Proceedings of the VLSI Design, Automation and Test, 2015

2014

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator.

Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2014

An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS.

Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin

Proceedings of the Symposium on VLSI Circuits, 2014