Tuotian Liao
Orcid: 0000-0003-0294-6804
According to our database1,
Tuotian Liao
authored at least 8 papers
between 2017 and 2022.
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Bibliography
2022
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2021
Efficient Parasitic-aware <i>g<sup>m</sup></i>/<i>I<sup>D</sup>-</i>based Hybrid Sizing Methodology for Analog and RF Integrated Circuits.
ACM Trans. Design Autom. Electr. Syst., 2021
An LDE-Aware g<sub>m</sub>/I<sub>D</sub>-Based Hybrid Sizing Method for Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2018
Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits.
Integr., 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Layout-dependent effects aware g<sub>m</sub>/i<sub>D</sub>-based many-objective sizing optimization for analog integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017