Tuo-Yu Yao

According to our database, Tuo-Yu Yao authored at least 2 papers between 2008 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology.

Chia-Hao Hsu, Gang-Neng Sung, Tuo-Yu Yao, Chun-Ying Juan, Yain-Reu Lin, Chua-Chin Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A ROM-less DDFS using a nonlinear DAC with an error compensation current array.

Chua-Chin Wang, Chia-Hao Hsu, Tuo-Yu Yao, Jian-Ming Huang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008