Tung-Liang Lin

According to our database, Tung-Liang Lin authored at least 3 papers between 2020 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

An Error Resilient Design Platform for Aggressively Reducing Power, Area and Routing Congestion.

Tung-Liang Lin, Sao-Jie Chen

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees.

Tung-Liang Lin, Sao-Jie Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations.

Tung-Liang Lin, Sao-Jie Chen

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020