Tung-Hua Yeh

According to our database, Tung-Hua Yeh authored at least 7 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

High-level low-power system design optimization.

David Pursley, Tung-Hua Yeh

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2014

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.

Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2012

Power-Aware High-Level Synthesis With Clock Skew Management.

Tung-Hua Yeh, Sying-Jyan Wang

IEEE Trans. Very Large Scale Integr. Syst., 2012

2010

Thermal Safe High Level Test Synthesis for Hierarchical Testability.

Tung-Hua Yeh, Sying-Jyan Wang

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability.

Sying-Jyan Wang, Tung-Hua Yeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2007

Test Data Compression for Minimum Test Application Time.

Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh

J. Inf. Sci. Eng., 2007

High-level test synthesis for delay fault testability.

Sying-Jyan Wang, Tung-Hua Yeh

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007