Tung-Chien Chen
According to our database1,
Tung-Chien Chen
authored at least 50 papers
between 2003 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
2014
Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem.
Proceedings of the IEEE International Conference on Acoustics, 2014
2013
IEEE Trans. Circuits Syst. Video Technol., 2013
Low-power multi-processor system architecture design for universal biomedical signal processing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
2011
Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC.
J. Signal Process. Syst., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Design and implementation of cubic spline interpolation for spike sorting microsystems.
Proceedings of the IEEE International Conference on Acoustics, 2011
Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology.
Proceedings of the IEEE International Conference on Acoustics, 2011
Seizure prediction based on classification of EEG synchronization patterns with on-line retraining and post-processing scheme.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Mobile energy expenditure tracking system based on heart rate and motion providing extra extensions for personalized care.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Robust heart rate measurement with phonocardiogram by on-line template extraction and matching.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
2010
Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices.
IEEE Trans. Circuits Syst. Video Technol., 2009
A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.
J. Signal Process. Syst., 2008
J. Signal Process. Syst., 2008
A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2007
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System.
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
IEEE Trans. Circuits Syst. Video Technol., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Analysis and architecture design of variable block-size motion estimation for H.264/AVC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder.
IEEE Trans. Circuits Syst. Video Technol., 2005
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Hardware architecture design for H.264/AVC intra frame coder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
2003
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003