Tung-Chieh Chen

Orcid: 0009-0000-3163-3634

According to our database¹, Tung-Chieh Chen authored at least 43 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

Introduction to the Panel on EDA Challenges at Advanced Technology Nodes.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Proceedings of the 2024 International Symposium on Physical Design, 2024

2022

Flexible Multiple-Objective Reinforcement Learning for Chip Placement.

[BibT_eX]

[DOI]

CoRR, 2022

Flexible chip placement via reinforcement learning: late breaking results.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Automatic Floorplanning for AI SoCs.

[BibT_eX]

[DOI]

Tai-Chen Chen

Pei-Yu Lee

Tung-Chieh Chen

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

2019

MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

FastPass: Fast timing path search for generalized timing exception handling.

[BibT_eX]

[DOI]

Pei-Yu Lee

Iris Hui-Ru Jiang

Tung-Chieh Chen

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Blockage-aware terminal propagation for placement wirelength minimization.

[BibT_eX]

[DOI]

Sheng-Wei Yang

Yao-Wen Chang

Tung-Chieh Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs.

[BibT_eX]

[DOI]

Szu-To Chen

Yao-Wen Chang

Tung-Chieh Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel damped-wave framework for macro placement.

[BibT_eX]

[DOI]

Chin-Hao Chang

Yao-Wen Chang

Tung-Chieh Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2015

A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An approach to anchoring and placing high performance custom digital designs.

[BibT_eX]

[DOI]

Shih-Ying Liu

Tung-Chieh Chen

Hung-Ming Chen

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

1-D Cell Generation With Printability Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Efficient analog layout prototyping by layout reuse with routing preservation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Lithography-aware 1-dimensional cell generation.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Routability-driven placement for hierarchical mixed-size circuit designs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Double patterning lithography-aware analog placement.

[BibT_eX]

[DOI]

Hsing-Chih Chang Chien

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Challenges and solutions in modern analog placement.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Performance-driven analog placement considering monotonic current paths.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Automated placement for custom digital designs.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Proceedings of the 2011 International Symposium on Physical Design, 2011

Fast analog layout prototyping for nanometer design migration.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009

Essential Issues in Analytical Placement Algorithms.

[BibT_eX]

[DOI]

Yao-Wen Chang

Zhe-Wei Jiang

Tung-Chieh Chen

IPSJ Trans. Syst. LSI Des. Methodol., 2009

2008

Packing Floorplan Representations.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yao-Wen Chang

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Metal-Density-Driven Placement for CMP Variation and Routability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yao-Wen Chang

Shyh-Chang Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Wire Models for X-Architecture Placement.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yi-Lin Chuang

Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An integrated nonlinear placement framework with congestion and porosity aware buffer planning.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Ashutosh Chakraborty

David Z. Pan

Proceedings of the 45th Design Automation Conference, 2008

2007

X-architecture placement based on effective wire models.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yi-Lin Chuang

Yao-Wen Chang

Proceedings of the 2007 International Symposium on Physical Design, 2007

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Modern Floorplanning Based on B<sup>*</sup>-Tree and Fast Simulated Annealing.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

NTUplace2: a hybrid placer using partitioning and analytical techniques.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Modern floorplanning based on fast simulated annealing.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yao-Wen Chang

Proceedings of the 2005 International Symposium on Physical Design, 2005

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Yao-Wen Chang

Shyh-Chang Lin

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

SoC test scheduling using the B-tree based floorplanning technique.

[BibT_eX]

[DOI]

Jen-Yi Wuu

Tung-Chieh Chen

Yao-Wen Chang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Tung-Chieh Chen

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...