Tun-Ju Wang

According to our database, Tun-Ju Wang authored at least 5 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration.

Chun-Yu Lin, Wei-Han Chen, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin

IEEE J. Solid State Circuits, November, 2024

2021

29.5 A 0.008mm² 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration.

Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique.

Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, Tsung-Hsien Lin

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

2017

An ultra-low power 169-nA 32.768-kHz fractional-N PLL.

Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.

Chun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017