Tsuyoshi Fujinaga

According to our database, Tsuyoshi Fujinaga authored at least 5 papers between 2009 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition.

Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.

Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2011

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.

Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2011

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.

Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system.

Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 10th Annual Conference of the International Speech Communication Association, 2009