Tsutomu Yoshihara

According to our database, Tsutomu Yoshihara authored at least 39 papers between 1988 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters.

Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara

IEICE Trans. Commun., 2016

2013

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System.

Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

IEEE J. Solid State Circuits, 2013

Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator.

Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

IEICE Trans. Electron., 2013

2012

An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme.

Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

High efficiency multi-channel LED driver based on SIMO switch-mode converter.

Luchen Yu, Yuan Zhu, Minjie Chen, Tsutomu Yoshihara

Proceedings of the International SoC Design Conference, 2012

A CMOS voltage reference combining body effect with switched-current technique.

Ning Ren, Hao Zhang, Tsutomu Yoshihara

Proceedings of the International SoC Design Conference, 2012

A novel charge recovery logic structure with complementary pass-transistor network.

Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara

Proceedings of the International SoC Design Conference, 2012

2011

An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic.

Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

IEICE Trans. Electron., 2011

An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory.

Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

IEICE Trans. Electron., 2011

A novel charge sharing charge pump for energy harvesting application.

Jiemin Zhou, Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara

Proceedings of the International SoC Design Conference, 2011

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic.

Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Word error control algorithm through multi-reading for NAND Flash memories.

Chong Zhang, Tsutomu Yoshihara

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A non-rectifier wireless power transmission system using on-chip inductor.

Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Double charge pump circuit with triple charge sharing clock scheme.

Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

CMOS low-power subthreshold reference voltage utilizing self-biased body effect.

Hao Zhang, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2008

2007

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2007

2005

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.

Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.

Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.

Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories.

Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

2004

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM.

Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2004

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree.

Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba

IEEE J. Solid State Circuits, 2001

2000

High-performance embedded SOI DRAM architecture for the low-power supply.

Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs.

Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki

IEEE J. Solid State Circuits, 2000

1994

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology.

Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1994

1990

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode.

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1990

A high-speed parallel sensing architecture for multi-megabit flash E/sup 2/PROMs.

Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1990

1989

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1989

A 5 V only one-transistor 256 K EEPROM with page-mode erase.

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, August, 1989

Analysis of coupling noise between adjacent bit lines in megabit DRAMs.

Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1989

Twisted bit-line architectures for multi-megabit DRAMs.

Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1989

1988

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1988