Tsung-Liang Chih

According to our database, Tsung-Liang Chih authored at least 3 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance.

Tong-Yu Hsieh, Tsung-Liang Chih, Mei-Jung Wu

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies.

Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement.

Tong-Yu Hsieh, Chih-Hao Wang, Chun-Wei Kuo, Shu-Yu Huang, Tsung-Liang Chih

J. Electron. Test., 2015