Tsung-Kai Kao

According to our database, Tsung-Kai Kao authored at least 3 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2016

15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique.

Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application.

Tsung-Kai Kao, Ping Chen, Jui-Yuan Tsai, Pao-Cheng Chiu

Proceedings of the Symposium on VLSI Circuits, 2015

2013

A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation.

Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013