SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs.

[BibT_eX]

[DOI]

Cho-Sheng Lin

Jing Huang

Po-Sheng Chang

Chun-Yen Tsai

Tsung-Chu Huang

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

AN-Coded Redundant Residue Number System for Reliable Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network.

[BibT_eX]

[DOI]

Wen-Chang Yang

Shu-Yun Lin

Tsung-Chu Huang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Approximate Computing for Batch Learning in Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Residue Number System Design Automation for Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

Low-Cost and Fast Design of Precise Activation Functions in Neural Network.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Chun-Hao Chiang

Mo-Han Lin

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

Self-Checking Residue Number System for Low-Power Reliable Neural Network.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Jeffae Schroff

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2015

Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes.

[BibT_eX]

[DOI]

Tsung-Chu Huang

IEEE Commun. Lett., 2015

2011

High-yield performance-efficient redundancy analysis for 2D memory.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Sci. China Inf. Sci., 2011

2010

HYPERA: High-Yield Performance-Efficient Redundancy Analysis.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Kuei-Yeh Lu

Yen-Chieh Huang

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Multi-valued equal-weight codes for self-checking and matching.

[BibT_eX]

[DOI]

Tsung-Chu Huang

IEEE Commun. Lett., 2009

2008

A Low-Power Dependable Berger Code for Fully Asymmetric Communication.

[BibT_eX]

[DOI]

Tsung-Chu Huang

IEEE Commun. Lett., 2008

2007

Congruence Synchronous Mirror Delay.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Gau-Bin Chang

Ling Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2002

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.

[BibT_eX]

[DOI]

Kuen-Jong Lee

Tsung-Chu Huang

J. Electron. Test., 2002

2001

Reduction of power consumption in scan-based circuits during testapplication by an input control technique.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Kuen-Jong Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A token scan architecture for low power testing.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Kuen-Jong Lee

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Low-Power LFSR Architecture.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Kuen-Jong Lee

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Peak-power reduction for multiple-scan circuits during test application.

[BibT_eX]

[DOI]

Kuen-Jong Lee

Tsung-Chu Huang

Jih-Jeen Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.

[BibT_eX]

[DOI]

Kuen-Jong Lee

Jing-Jou Tang

Tsung-Chu Huang

ACM Trans. Design Autom. Electr. Syst., 1999

An Input Control Technique for Power Reduction in Scan Circuits During Test Application.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Kuen-Jong Lee

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1997

Built-in current sensor designs based on the bulk-driven technique.

[BibT_eX]

[DOI]

Tsung-Chu Huang

Min-Cheng Huang

Kuen-Jong Lee

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.

[BibT_eX]

[DOI]

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Tsung-Chu Huang

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