Tsung-Chih Hung
Orcid: 0000-0002-8038-7289
According to our database1,
Tsung-Chih Hung
authored at least 8 papers
between 2016 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique.
IEEE J. Solid State Circuits, 2020
16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Feasibility Study of Introducing Daily Rental Suites Business Model into Long-Term Care Institutions.
Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2020
2019
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch.
IEEE J. Solid State Circuits, 2019
A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2016
A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016