Tsuneo Inaba

According to our database, Tsuneo Inaba authored at least 4 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.

Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2010

A 64Mb MRAM with clamped-reference and adequate-reference schemes.

Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

Resistance ratio read (R³) architecture for a burst operated 1.5V MRAM macro.

Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003