Tsukasa Yamauchi

According to our database1, Tsukasa Yamauchi authored at least 7 papers between 1991 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2001
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1998
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

Evolvable Hardware Chip for High Precision Printer Image Compression.
Proceedings of the Fifteenth National Conference on Artificial Intelligence and Tenth Innovative Applications of Artificial Intelligence Conference, 1998

1996
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.
Proceedings of the Parcella 1996, 1996

SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1991
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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