Tsukasa Shirotori

According to our database, Tsukasa Shirotori authored at least 6 papers between 1988 and 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1994

A 110-MHz/1-Mb synchronous TagRAM.

Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman

IEEE J. Solid State Circuits, April, 1994

1993

A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture.

Tsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto

IEEE J. Solid State Circuits, April, 1993

1991

A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation.

Tsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto, Yoshitaka Biwaki, Haruo Nohara, Makiji Kobayashi, Kiyoshi Kobayashi, Kazuhiro Sawada

IEEE J. Solid State Circuits, November, 1991

1990

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC.

Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka

IEEE J. Solid State Circuits, February, 1990

1989

A 32 kbyte integrated cache memory.

Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato

IEEE J. Solid State Circuits, August, 1989

1988

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode.

Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka

IEEE J. Solid State Circuits, February, 1988