Tsin-Yuan Chang

IEEE Trans. Very Large Scale Integr. Syst., 2012

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems.

[BibT_eX]

[DOI]

Song-Nien Tang

Chi-Hsiang Liao

IEEE J. Solid State Circuits, 2012

2011

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

2010

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications.

[BibT_eX]

[DOI]

Song-Nien Tang

Jui-Wei Tsai

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500.

[BibT_eX]

[DOI]

Po-Lin Chen

Yu-Chieh Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

IEEE Standard 1500 Compatible Delay Test Framework.

[BibT_eX]

[DOI]

Po-Lin Chen

Jhih-Wei Lin

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement.

[BibT_eX]

[DOI]

Hung-Chih Lin

Hsiang-Han Wu

IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A current mode adaptive on-time control scheme for fast transient DC-DC converters.

[BibT_eX]

[DOI]

Hung-Chih Lin

Bou-Ching Fung

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

A chaos-based pseudo random number generator using timing-based reseeding method.

[BibT_eX]

[DOI]

Jiung-Sheng Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range.

[BibT_eX]

[DOI]

Chia-yuan Chou

Proceedings of the 15th Asian Test Symposium, 2006

2005

On-chip accumulated jitter measurement for phase-locked loops.

[BibT_eX]

[DOI]

Chih-Feng Li

Shao-Sheng Yang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Built-In Parametric Timing Measurement Unit.

[BibT_eX]

[DOI]

Jing-Reng Huang

IEEE Des. Test Comput., 2004

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.

[BibT_eX]

[DOI]

Yi-Ming Sheng

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Timing measurement unit with multi-stage TVC for embedded memories.

[BibT_eX]

[DOI]

Kae-Jiun Mo

Shao-Sheng Yang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

An Access Timing Measurement Unit of Embedded Memory.

[BibT_eX]

[DOI]

Shu-Rong Lee

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.

[BibT_eX]

[DOI]

Sheng-Hung Hsieh

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A built-in timing parametric measurement unit.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A low-cost CMOS time interval measurement core.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.

[BibT_eX]

[DOI]

Jeng-Horng Tsai

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A realistic fault model for flash memories.

[BibT_eX]

[DOI]

Yea-Ling Horng

Jing-Reng Huang

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

SoC Testing and P1500 Standard.

[BibT_eX]

[DOI]

Yervant Zorian

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Programmable BIST Core for Embedded DRAM.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1999

1992

A design for concurrent error detections in FPLAs.

[BibT_eX]

[DOI]

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990

An efficient output phase assignment for PLA minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.

[BibT_eX]

[DOI]

Jyhyeung Ding

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Design of fault diagnosable and repairable PLA's.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 1989

1988

PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.

[BibT_eX]

[DOI]