Tse-Yu Yeh

According to our database1, Tse-Yu Yeh authored at least 14 papers between 1991 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.
IEEE Micro, 2016

2014
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2007
Low-Power, High-Performance Architecture of the PWRficient Processor Family.
IEEE Micro, 2007

2001
Understanding branches and designing branch predictors for high-performance microprocessors.
Proc. IEEE, 2001

1998
Alternative Implementations of Two-Level Adaptive Branch Prediction.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1996
Branch Classification: New Mechanism for Improving Branch Predictor Performance.
Int. J. Parallel Program., 1996

1993
Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors.
PhD thesis, 1993

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.
Proceedings of the 7th international conference on Supercomputing, 1993

1992
A comprehensive instruction fetch mechanism for a processor supporting speculative execution.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991
Two-Level Adaptive Training Branch Prediction.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Single Instruction Stream Parallelism is Greater Than Two.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991


  Loading...