Tse-Ching Wu

According to our database, Tse-Ching Wu authored at least 2 papers in 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.

Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.

Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang

Proceedings of the 2015 International Conference on IC Design & Technology, 2015