Tsang-Chi Kan

According to our database, Tsang-Chi Kan authored at least 8 papers between 2010 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration.

Tsang-Chi Kan, Shanq-Jang Ruan, Ting-Feng Chang, Shih-Hsien Yang

Circuits Syst. Signal Process., 2015

2014

Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration.

Tsang-Chi Kan, Ying-Jung Chen, Hung-Ming Hong, Shanq-Jang Ruan

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013

Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate.

Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan

IEEE Trans. Very Large Scale Integr. Syst., 2013

Configurable redundant via-aware standard cell design considering multi-via mechanism.

Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, Shanq-Jang Ruan

Proceedings of the International Symposium on Quality Electronic Design, 2013

Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning.

Chih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan

Proceedings of the International Symposium on Quality Electronic Design, 2013

2011

Enhanced Redundant via Insertion with Multi-via Mechanisms.

Ting-Feng Chang, Tsang-Chi Kan, Shih-Hsien Yang, Shanq-Jang Ruan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Nanometer-scale standard cell library for enhanced redundant via1 insertion rate.

Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.

Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010