Tsai-Ming Hsieh

According to our database¹, Tsai-Ming Hsieh authored at least 20 papers between 2000 and 2016.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2016

Unified approach for simultaneous functional and timing ECO.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2016

2015

A logic difference generator with spare cells consideration for ECO synthesis.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2012

Image Retrieval based on color and texture features.

[BibT_eX]

[DOI]

Chin-Hung Su

Mohd Helmy Abd Wahab

Tsai-Ming Hsieh

Proceedings of the 9th International Conference on Fuzzy Systems and Knowledge Discovery, 2012

2011

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A new ECO technology for functional changes and removing timing violations.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Technology remapping for engineering change with wirelength consideration.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008

Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Timing-driven X-architecture router among rectangular obstacles.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

A congestion-driven buffer planner with space reservation.

[BibT_eX]

[DOI]

Hsin-Hsiung Huang

Yung-Ching Chen

Tsai-Ming Hsieh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A new congestion and crosstalk aware router.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Floorplanning with clock tree estimation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A New Effective Congestion Model in Floorplan Design.

[BibT_eX]

[DOI]

Yi-Lin Hsieh

Tsai-Ming Hsieh

Proceedings of the 2004 Design, 2004

2002

Structural Decomposition with Functional Considerations for Low Power.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Sequence-pair based placement with boundary constraints.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A New Formulation for SOC Floorplan Area Minimization Problem.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

An efficient hierarchical approach for general floorplan area minimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Minimum crosstalk channel routing with dogleg.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract).

[BibT_eX]

[DOI]

Yu-Chung Lin

Su-Feng Tseng

Tsai-Ming Hsieh

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Tsai-Ming Hsieh

Timeline

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On csauthors.net:

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