Trong-Thuc Hoang
Orcid: 0000-0002-4078-0836
According to our database1,
Trong-Thuc Hoang
authored at least 74 papers
between 2015 and 2024.
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Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme.
Inf., July, 2024
Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications.
Future Internet, May, 2024
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
IEEE Access, 2024
IEEE Access, 2024
Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System.
IEEE Access, 2024
Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps.
IEEE Access, 2024
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding.
Proceedings of the Computational Science and Its Applications - ICCSA 2024 Workshops, 2024
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
2023
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.
IEEE Trans. Computers, September, 2023
A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography.
Cryptogr., September, 2023
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.
Future Internet, May, 2023
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.
Comput. Electr. Eng., January, 2023
IEEE Access, 2023
FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V.
Proceedings of the International Conference on Computing and Communication Technologies, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Future Internet, 2022
ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3.
Cryptogr., 2022
IEEE Access, 2022
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.
IEEE Access, 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.
IEICE Electron. Express, 2021
A proposal for enhancing training speed in deep learning models based on memory activity survey.
IEICE Electron. Express, 2021
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.
IEEE Access, 2021
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor.
IEEE Access, 2021
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure.
IEEE Access, 2021
Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks.
IEEE Access, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
2020
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.
Microprocess. Microsystems, 2020
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.
Microprocess. Microsystems, 2019
A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC.
IEICE Electron. Express, 2019
A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC.
Proceedings of the IEEE International Conference on Industrial Technology, 2019
2018
IEICE Electron. Express, 2018
Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC.
IEICE Electron. Express, 2018
IEEE Access, 2018
VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEICE Electron. Express, 2015
Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese.
IEICE Electron. Express, 2015