Trong-Thuc Hoang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2023

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Trong-Hung Nguyen

Cryptogr., September, 2023

A Survey of Post-Quantum Cryptography: Start of a New Race.

[BibT_eX]

[DOI]

Cryptogr., July, 2023

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.

[BibT_eX]

[DOI]

Future Internet, May, 2023

A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.

[BibT_eX]

[DOI]

Comput. Electr. Eng., January, 2023

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor.

[BibT_eX]

[DOI]

IEEE Access, 2023

FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing and Communication Technologies, 2023

Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Unified PUF and Crypto Core Exploiting the Metastability in Latches.

[BibT_eX]

[DOI]

Future Internet, 2022

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3.

[BibT_eX]

[DOI]

Cryptogr., 2022

Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA.

[BibT_eX]

[DOI]

Cryptogr., 2022

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse.

[BibT_eX]

[DOI]

IEEE Access, 2022

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.

[BibT_eX]

[DOI]

IEEE Access, 2022

High-performance Multi-function HMAC-SHA2 FPGA Implementation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Spectre attack detection with Neutral Network on RISC-V processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-speed FPGA-based Design and Implementation of Text Search Processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2022

A System-on-Chip for IoT Applications with 16-bit Tiny Processor.

[BibT_eX]

[DOI]

Tuan-Kiet Dang

Khai-Duy Nguyen

Proceedings of the International Conference on IC Design and Technology, 2022

2021

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.

[BibT_eX]

[DOI]

Khai-Duy Nguyen

Tuan-Kiet Dang

Xuan-Tu Tran

IEICE Electron. Express, 2021

A proposal for enhancing training speed in deep learning models based on memory activity survey.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor.

[BibT_eX]

[DOI]

IEEE Access, 2021

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure.

[BibT_eX]

[DOI]

IEEE Access, 2021

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Khai-Duy Nguyen

Tuan-Kiet Dang

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2020

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

Quick Boot of Trusted Execution Environment With Hardware Accelerators.

[BibT_eX]

[DOI]

Ckristian Duran

Duc-Thinh Nguyen-Hoang

IEEE Access, 2020

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Industrial Technology, 2019

2018

A CORDIC-based QR decomposition for MIMO signal detector.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

Frequent items counter based on binary decoders.

[BibT_eX]

[DOI]

Katsumi Inoue

IEICE Electron. Express, 2018

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation.

[BibT_eX]

[DOI]

IEEE Access, 2018

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.

[BibT_eX]

[DOI]

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC.

[BibT_eX]

[DOI]